Oct 23, 2017 - The Intel Processor Identification Utility allows you to identify the brand. Intel Celeron Processor G540 (2M Cache, 2.50 GHz); Intel Celeron. Support Home Drivers & Software. Downloads for Intel® Celeron® Processor G540 (2M Cache, 2.50 GHz). The Intel® Processor Identification Utility is provided.

Top of a Sandy Bridge i5 Sandy Bridge is the for the microarchitecture used in the 'second generation' of the (,, ) - the Sandy Bridge microarchitecture is the successor to. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the brand. Developed primarily by the branch of Intel, the codename was originally 'Gesher' (: גשר‎; meaning 'bridge' in ). Sandy Bridge is manufactured in the process, while Intel's subsequent generation (announced 2011) uses a. This was known as the. A Core i7 2600 Sandy Bridge CPU at 3.4 GHz with 1333 MHz DDR3 memory reaches 83 performance in the benchmark and 118,000 in the benchmark. It is the last Intel microarchitecture for which driver support officially exists.

Contents • • • • • • • • • • • • • • • • • • • • • Technology [ ] Developed primarily by the branch of, the codename was originally 'Gesher' (meaning 'bridge' in ). The name was changed to avoid being associated with the defunct; the decision was led by Ron Friedman, vice president of Intel managing the group at the time. Intel demonstrated a Sandy Bridge processor with A1 at 2 during the in September 2009. Upgraded features from Nehalem include: • Intel Turbo Boost 2.0 • 32 KB data + 32 KB instruction (4 clocks) and 256 KB (11 clocks) per core • Shared L3 cache includes the processor graphics (). • 64-byte line size • Improved 3 integer ALU, 2 vector ALU and 2 AGU per core.

• Two load/store operations per for each memory channel • Decoded (uop cache) and enlarged, optimized • Sandy Bridge retains the four branch predictors found in Nehalem: the (BTB), indirect branch target array, loop detector and renamed (RSB). Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem.

• Improved performance for, (), and hashing • 256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain • (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality. •, hardware support for video encoding and decoding • Up to eight physical cores or 16 logical cores through • Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor,, has two separate dies (one for GMCH, one for processor) within the processor package.